A stream of address 6, 7, 6, 5, 9, 6, 8, 9, 7, 6 is to be entered serially into the cache memory which can only contain 3 page addresses at a time. Show this using the LRU replacement policy.
LRU Replacement Policy
A stream of address 6, 7, 6, 5, 9, 6, 8, 9, 7, 6 is to be entered serially into the cache memory which can only contain 3 page addresses at a time. Show this using the LRU replacement policy.
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